MTL or I.sup.2 L memory cells are now well known. For example, in commonly assigned U.S. Pat. No. 4,158,237, filed on July 13, 1978, by S. K. Wiedmann, there is disclosed an MTL or I.sup.2 L cell which includes a flip-flop circuit having two cross-coupled bipolar switching transistors with a pair of load or injector elements, one of which is connected to the base of one of the cross-coupled transistors and to the collector of the other cross-coupled transistor and the other load or injector element is connected to the base of the other cross-coupled transistor and to the collector of the one cross-coupled transistor. The cell is controlled or accessed via a single word line connected to the cross-coupled transistors through both load or injector elements and first and second bit/sense lines, with the first bit/sense line being connected to the emitter of the one cross-coupled transistor and the second bit/sense line being connected to the emitter of the other cross-coupled transistor. The cross-coupled transistors are NPN transistors and the load or injector elements are PNP transistors.
To reduce access time in arrays employing the MTL type cells, it is known to discharge the bit/sense line capacitance before selection in order to reduce the differential voltage developed between a given pair of bit/sense lines, which voltage is dependent on the state of the cells connected to the given bit/sense line pair. Individual bit line transistor means coupled to each bit line for reducing the access time is taught in commonly assigned U.S. Pat. No. 4,280,198, filed by K. Heuber and S. K. Wiedmann on Dec. 7, 1979. Other bipolar circuits which have been used to balance the differential voltage between a pair of bit/sense lines are disclosed in commonly assigned U.S. Pat. No. 4,090,255, filed by H. H. Berger, K. Heuber, W. Klein, K. Najmann and S. Wiedmann on Mar. 1, 1976, and U.S. Pat. No. 4,302,823, filed by J. E. Gersbach and I. W. Kim on Dec. 27, 1979, and in U.S. Pat. No. 3,786,442, filed by S. B. Alexander, R. W. Bryant, R. J. Lipp and G. K. Tu on Feb. 24, 1972. Field effect transistor circuits, as described, e.g., in commonly assigned U.S. Pat. No. 3,949,383, filed by H. O. Askin, E. C. Jacobson, J. M. Lee and G. Sonoda on Dec. 23, 1974, and in U.S. Pat. No. 4,272,834, filed by Y. Noguchi and T. Ito on Oct. 3, 1979, have also been used to balance the differential voltage developed between a pair of bit/sense lines coupled to a column of field effect transistor memory cells.